1. Field of the Invention
The present invention relates to a technique relating to a semiconductor device formed over a substrate.
2. Description of the Related Art
At present, semiconductor memory devices for a personal computer, a digital camera, a mobile phone device, a household electrical appliance, an RFID, and the like have been actively developed. In particular, various configurations and structures have been researched and developed mainly on an EEPROM, and a flash memory each having a floating gate structure. Techniques in which a semiconductor memory device is formed not only over a silicon wafer but over a glass substrate, a plastic substrate, and a silicon wafer including an insulating layer have also been developed. Such a semiconductor memory device is disclosed, for example, in Reference 1 (Japanese Published Patent Application No. Hei 5-82787) and the like. A structure of a semiconductor memory device disclosed in Reference 1 and the like is described with reference to FIGS. 12A to 12D.
A semiconductor memory device shown in FIG. 12A is disclosed in FIG. 1 of Reference 1. The semiconductor memory device of FIG. 12A has a semiconductor layer 1003 having a channel forming region 1003a and a source or drain region 1003b, a tunnel insulating film 1004, a floating gate electrode 1005, a middle insulating film 1006, and a control gate electrode 1007 over a semiconductor substrate 1000 over which an insulating film 1002 is formed.
On the other hand, a semiconductor memory device as shown in FIG. 12C is disclosed in FIG. 2 of Reference 1 and Reference 2 (Japanese Published Patent Application No. Hei 11-87545). Here, the semiconductor layer 1003, the tunnel insulating film 1004, the floating gate electrode 1005, a middle insulating film 1006, and the control gate electrode 1007 are formed over the semiconductor substrate 1000 over which the insulating film 1002 is formed. As shown in FIG. 12D, the semiconductor layer 1003, an insulating film 1004a, a floating gate layer 1005a, an insulating film 1006a, and a control gate layer 1007a are formed, and then collectively etched by using a resist mask 1008.